The Product Failure Analysis Engineer - SCAN Design for Test at Intel will play a crucial role in enhancing the quality and ramp of Intel Foundry's advanced technology. This position requires a candidate with 6-12 years of semiconductor experience, particularly in DFT, ATPG, and silicon debug. The engineer will collaborate with various teams to identify and resolve silicon failures, driving improvements in product quality and reliability. The role also involves developing innovative methodologies and automation frameworks to enhance debug efficiency.

• Bachelor’s degree in electrical engineering, computer engineering, or a related STEM discipline with 6+ years of hands-on experience, OR master's degree with 4+ years, OR PhD with 2+ years.
• Expertise in Design for Test (DFT) tools and techniques, SCAN ATPG methodology, and Scan Chain Diagnosis.
• Experience with Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, simulation and diagnosis tools.
• Hands-on experience developing debug automation and analysis tools using Python, Perl, or TCL.

• Utilize state-of-the-art lab equipment to isolate microscopic silicon circuit failures and identify root causes.
• Partner with test and validation engineers, circuit designers, and manufacturing teams to resolve quality issues.
• Develop new debug tools, methodologies, and technologies that enhance silicon debug.
• Evaluate and resolve component engineering and physical design issues to ensure design-for-debug features.
• Provide expert input on failure analysis investigation areas and design process improvements.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.