The ASIC Power Engineer for ML Accelerators at Google will focus on enhancing the power efficiency of Tensor Processing Units (TPUs) that drive AI/ML applications. This role involves collaborating with a team dedicated to developing custom silicon solutions and optimizing power management architectures. The engineer will leverage their expertise in silicon design and power modeling to contribute to innovative designs that meet power goals. This position is part of a dynamic team that is redefining AI and infrastructure capabilities at Google.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in silicon design or architecture, including logic design, power architecture, performance, or SoC design.
• Experience with power design, power modeling, power architecture, or power reduction methodologies.

• Contribute to design power modeling and drive convergence to power goals.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.