The Senior DFT Design Engineer role at Intel focuses on making significant impacts in graphics and visual computing. As part of the GPU Hardware IP team within the Data Center Group, the engineer will work on design, validation, and automation for Scan/ATPG. The position involves developing logic design and RTL coding for graphics IPs and ensuring high-quality integration of GPU blocks. This role is ideal for those passionate about innovation in visual computing and contributing to impactful technologies.

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 4+ years of industry experience, or a Master's degree with 3+ years of experience, or a PhD with 1+ year of experience.
• Experience in Scan, ATPG, or other DFT features.
• Experience in SoC or IP DFT design, integration, or verification.
• Familiarity with EDA tools such as Siemens Tessent or other ATPG tools, Synopsis VCS, and/or other simulation or debug tools.

• Work on the design, RTL/GLS validation, automation, and timing analysis for Scan/ATPG.
• Contribute to trace/pattern generation efforts and post-silicon enabling, debug support, and analysis of ATPG content.
• Develop logic design, RTL coding, and simulation for graphics IPs required for full chip designs.
• Participate in defining architecture and microarchitecture features of the block being designed.
• Review the verification plan and implementation to ensure design features are verified correctly.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.