Job description
This role at Apple involves converting RTL designs into netlists and optimizing power, performance, and area through synthesis methodologies. The position requires a strong understanding of Verilog and SystemVerilog, as well as the ability to perform various checks to ensure design robustness and correctness. Collaboration with internal R&D teams is essential to develop optimal RTL solutions. The role is based in Austin, Texas and requires a commitment of 40 hours per week.
Requirements
- Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field
- 1 year of experience in the job offered or related occupation
- Experience synthesizing RTL designs using Design Compiler/Genus into netlist
- Understanding RTL and making RTL updates for power, performance, and area (PPA)
- Experience creating unit testbenches to verify RTL updates
- Experience performing Static Timing Analysis (STA) and achieving timing closure
- Experience performing Lint checks to ensure RTL quality
- Experience performing Clock Domain Crossing checks (CDC)
- Experience performing Reset Domain Crossing checks (RDC)
Responsibilities
- Convert RTL designs into netlists using industry-standard RTL synthesis tools.
- Optimize power, performance, and area by experimenting with synthesis recipes.
- Understand RTL code written in Verilog and SystemVerilog and correlate it to gate-level circuits.
- Perform Clock and Reset Domain Crossing (CDC, RDC) checks to ensure design robustness.
- Conduct logical equivalence checks to ensure correctness of the generated netlist.
- Support ECO generation activities and perform static timing analysis to identify critical paths.
- Analyze RTL simulation waveforms using industry-standard simulator tools.
- Collaborate effectively with internal R&D teams.
Benefits
- Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.
H-1B filing history
Public USCIS petition and DOL LCA counts · latest USCIS FY2026, LCA FY2026
Filing entity: Apple Inc
As of Aug 23, 2026
Initial approvals
1,065
FY2026
Approval rate
99.0%
FY2026
LCA certified
9,221
FY2026
Entry-level share
5.6%
FY2026
Initial approvals YoY
+30%
Trend
LCA certified YoY
-35%
Trend
Initial approvals by fiscal year
Approval rate by fiscal year
Continuing vs initial approvals
LCA certified positions by quarter
LCA certified positions by fiscal year
Based on public USCIS and DOL filings; not a sponsorship guarantee.
Is this posting expired or inaccurate?
