Job description
This role at Apple focuses on microarchitecture definition and RTL design in SystemVerilog/Verilog within a collaborative team environment. The position emphasizes IP integration and verification, ensuring low-power design and performance efficiency. Candidates will work closely with system, algorithm, and firmware teams to achieve design goals. This opportunity is based in San Diego, California, and offers a comprehensive compensation package.
Requirements
- Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Communication Engineering, or a related field.
- 3 years of experience in the job offered or a related occupation.
- Experience utilizing System Verilog or Verilog to write RTL for high-speed communication IPs.
- Proficiency in scripting languages such as Python, Perl, or TCL for automating RTL integration and verification.
- Knowledge of CDC and RDC tools/techniques, including handling multiple clock and reset domains.
Responsibilities
- Define microarchitecture and perform RTL design in SystemVerilog/Verilog.
- Integrate and verify IP while ensuring a lint-free and CDC clean design.
- Run tools for RTL power analysis and implement low-power design techniques.
- Collaborate with system, algorithm, and firmware teams to optimize performance and power efficiency.
- Set synthesis and timing constraints while utilizing synthesis tools from Synopsys and Cadence.
Benefits
- Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.
H-1B filing history
Public USCIS petition and DOL LCA counts · latest USCIS FY2026, LCA FY2026
Filing entity: Apple Inc
As of Aug 23, 2026
Initial approvals
1,065
FY2026
Approval rate
99.0%
FY2026
LCA certified
9,221
FY2026
Entry-level share
5.6%
FY2026
Initial approvals YoY
+30%
Trend
LCA certified YoY
-35%
Trend
Initial approvals by fiscal year
Approval rate by fiscal year
Continuing vs initial approvals
LCA certified positions by quarter
LCA certified positions by fiscal year
Based on public USCIS and DOL filings; not a sponsorship guarantee.
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