This position at Apple focuses on building full chip clock trees and automating clock tree specification generation. The role involves collaborating with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. The candidate will conduct verification and drive signoff closure for partitions while resolving design and flow issues. This position is based in San Diego, California, and requires a strong background in physical design and clock network optimization.

• Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
• 2 years of experience in the job offered or a related occupation.
• Experience in building clock networks for high-performance CPU cores.
• Knowledge of analyzing interconnect delays, parasitics, and coupling.
• Experience with FinFET and GAA standard cell technologies.

• Build full chip clock trees and perform specification generation.
• Automate clock tree specification generation for clock construction and distribution.
• Work with the logic design team to understand partition architecture.
• Complete netlist to GDS2 implementation for partitions meeting schedule and design goals.
• Conduct timing, physical, and electrical verification, and drive signoff closure.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.