This role at Apple involves contributing to the physical design of high-performance PHY design from RTL to GDSII delivery. The position requires collaboration with a diverse team to innovate and create products that enhance user experiences. The focus is on ensuring design quality and performance through various methodologies and tools. Candidates will engage in both technical and strategic aspects of physical design, including timing, area, and power constraints.

• Master's degree or foreign equivalent in Electrical Engineering or a related field.
• Experience in identifying root-cause LVS DRC ERC issues and closing PDV.
• Proficiency in Tcl, Perl, and Python scripting for physical design data mining.
• Knowledge of low power techniques such as clock gating and power gating.
• Experience with EMIR analysis to address hot spot violations.

• Contribute to all phases of the physical design process from RTL to GDSII.
• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement and power grid.
• Develop and validate high performance low power clock network guidelines.
• Run Physical Design verification flow at chip/block level.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.