Intel is seeking a motivated SoC Validation Engineer to join the Power Management Validation team. This role focuses on validating power management architectures and features for Intel's next-generation products. The engineer will ensure design quality, functionality, and power efficiency through innovative validation strategies and comprehensive test plans. This position offers the opportunity to influence future Intel products while expanding technical leadership and validation expertise.

• Bachelor's degree with 6+ years of experience, Master's degree with 4+ years, or PhD with 2+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.
• Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.
• Strong knowledge of SystemVerilog and UVM-based validation methodologies.
• Experience with simulation or emulation environments, debugging, and root-cause analysis skills.
• Knowledge in Python, Perl, Shell, or similar scripting languages.

• Develop and execute comprehensive validation plans to ensure power management features meet architectural and functional specifications.
• Design, develop, and maintain validation environments, automated test content, and debug infrastructure for power management validation.
• Validate critical power management features including Dynamic Voltage and Frequency Scaling (DVFS), Power Gating, and Clock Gating.
• Develop validation content and infrastructure using industry-standard methodologies and tools such as SystemVerilog and UVM.
• Execute simulation and emulation workloads to validate design functionality and identify issues early in the product development cycle.
• Analyze validation results, coverage metrics, and performance data to improve design quality and validation effectiveness.
• Drive root cause analysis, debug, and resolution of complex design issues in collaboration with architecture, RTL design, and verification teams.
• Develop and maintain automation frameworks, regression environments, dashboards, and data analysis tools to improve validation efficiency and coverage.
• Review architecture specifications and design changes to assess validation impact and ensure comprehensive feature coverage.
• Contribute to validation methodology improvements and best practices across multiple product generations.
• Mentor junior engineers and provide technical leadership on complex validation and debug challenges.
• Continuously explore new technologies, automation techniques, and AI-assisted solutions to improve execution and outcomes.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.