AMD is seeking a Senior Member of Technical Staff (SMTS) Silicon Design Engineer to join the CDFX Design Verification (DV) team. The role focuses on DFT IP verification, including test plan creation, development, and execution. The engineer will lead DV projects, ensuring timely completion while providing technical support to internal SOC teams. This position allows for remote work and involves collaboration with cross-functional technical leaders to enhance DFX DV strategy.

• Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electrical and Electronics Engineering, or related field.
• Four years of experience in the job offered or closely related engineering role.
• Alternatively, a Bachelor's degree or foreign equivalent in the same fields with six years of progressive post-baccalaureate experience.

• Perform DFT IP verification, including IP level test plan creation and development.
• Conduct and participate in test plan reviews.
• Develop scalable verification components and random-constrained stimulus.
• Debug regression failures and perform code reviews.
• Lead DV execution, including project planning, delivery timelines, and quality checks.
• Track project progress to ensure timely completion.
• Provide technical support to SOC teams on DFT IP deliverables and tape out readiness signoff.
• Collaborate with cross-functional DV technical leaders to drive DFX DV strategy.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.