The MTS Silicon Design Engineer at Xilinx, a subsidiary of AMD, is responsible for researching, designing, developing, and testing electronic components and systems for semiconductor manufacturing. This role involves overseeing custom mixed-signal design development and working with cross-functional teams to resolve complex issues. The engineer will utilize their knowledge of electronic theory and engineering principles to drive significant technical projects. The position emphasizes the importance of innovation in technology to advance AMD's product offerings.

• Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field.
• Three years of experience in the job offered or a related engineering role.
• Alternatively, a Bachelor's degree or foreign equivalent in a related field and five years of progressive post-baccalaureate experience in the job offered or a closely related engineering role.
• Experience in mixed-signal circuit design, low power design techniques, and functional verification of microprocessors.
• Proficiency in C, C++, or Python and familiarity with Unix or Linux environments.

• Research, design, develop, and test electronic components and systems for semiconductor manufacturing.
• Oversee definition, design, verification, and documentation for custom mixed-signal design development.
• Determine architecture design, logic design, and system simulation.
• Lead the development of multidimensional designs involving the layout of complex integrated circuits.
• Participate in product bring-up and debug, contributing to test plans and characterization reports.
• Evaluate all aspects of the process flow from high-level designs to synthesis, place and route, and timing and power use.
• Work with cross-functional teams to develop custom mixed signal/layout designs.
• Drive projects or processes of significant technical importance.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.