The role is focused on mixed signal high-speed PHY post-silicon validation and debug within Intel's Hard IP Development Group. The team is responsible for developing leadership IPs for various SOCs and engages with both IP design teams and SOC customers. This position offers the opportunity to utilize expertise in mixed signal design and post-silicon debug across multiple IPs. The role involves generating test plans, conducting SOC board design reviews, and resolving customer issues.

• BS with 6+ years, MS with 4+ years, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.
• Relevant experience in electrical or bench post-silicon validation with high-speed PHYs such as PCIe, USB, UCIe, DDR, or Ethernet.
• Experience with lab hardware and software including Oscilloscopes, Logic Analyzers, Protocol Analyzers, and BERTs.
• Knowledge of one or more industry-standard IO specifications such as PCIe, USB, or Die-to-Die UCIe.

• Generate test plans and test content for mixed signal high-speed PHY post-silicon validation.
• Perform IO protocol debug across PCIe, UCIe, DDR, or Ethernet from both PHY recipe and firmware perspectives.
• Conduct SOC board design reviews and provide recommendations.
• Represent the IP team during SOC Power-Ons for test chips and products.
• Identify clocking and PHY-related silicon issues and investigate customer bugs.
• Reproduce customer issues and drive root cause analysis through structured debug methodologies.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.