The role is for a senior technical leader in the AMS Design-Technology Co-Optimization (DTCO) team at Intel, focusing on the co-optimization of next-generation process technologies for analog, mixed-signal, and custom design. This team operates at the intersection of process technology, design rules, PDK, EDA tools, and circuit design. The position requires collaboration with various teams and external EDA partners to ensure competitive performance and productivity. The individual will also mentor engineers and set technical direction for the DTCO team.

• 5+ years of DTCO experience for analog, mixed-signal, I/O, or custom design on FinFET or more advanced process nodes.
• Experience in design-rule definition for analog or custom layout.
• Experience in circuit-level technology benchmarking of analog or mixed-signal building blocks.
• Experience in EDA tool or flow enablement of analog and custom design for a new process node.
• Advanced degree in Electrical Engineering, Computer Engineering, Materials Science, Physics, or a related field.

• Lead AMS DTCO for future Intel Foundry nodes by evaluating device architecture and design rules.
• Run a closed-loop DTCO process to sense issues from designers and prioritize changes.
• Quantify technology impact on circuits through layout studies and performance scaling analysis.
• Define and drive design-rule and PDK requirements with various teams.
• Partner with EDA vendors on node enablement for custom and AMS flows.
• Represent Intel Foundry in technical engagements with EDA partners and customers.
• Mentor engineers and set technical direction for the DTCO team.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.