The ASIC Design Verification Engineer for Machine Learning at Google will focus on shaping the future of AI/ML hardware acceleration, specifically working on TPU technology that powers demanding applications. This role involves verifying complex digital designs and contributing to the development of custom silicon solutions. The engineer will be part of a dynamic team that is redefining capabilities in AI and infrastructure, ensuring the delivery of high-performance computing solutions. Responsibilities will include project definition, design verification, and silicon bring-up.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science is preferred.
• 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to ensure functionally correct design blocks.
• Close coverage measures to identify verification holes and demonstrate progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.