The SoC Silicon Top-Level Floorplan Engineer at Google will play a crucial role in shaping the future of AI and ML hardware acceleration. This position involves driving the development of cutting-edge TPU technology that supports Google's most demanding applications. The engineer will collaborate with various teams to create and deliver top-level floorplan designs for SoCs, ensuring optimal performance, power, and area. This role requires deep expertise in silicon design and a commitment to innovation in hardware solutions.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in Silicon/ASIC design flows and methodologies.
• 5 years of experience in top level floorplanning/integration roles with multiple levels of hierarchy and assembly.
• Experience planning, owning, and delivering top-level floorplan designs for SoCs in advanced nodes.
• Experience managing cross-functional interactions related to top-level floorplanning of chip projects.

• Own the planning, creation and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.
• Resolve structural or physical issues related to the integration of complex ASICs and SOCs and collaborate with teams across Google to develop ideas for high impact Silicon and hardware projects.
• Manage all cross-functional interactions related to top-level floorplanning of chip projects.
• Develop and improve floorplan implementation methodologies.
• Perform technical evaluations of vendors and IP, providing recommendations and assessment of process node tradeoffs to meet performance, power, area and cost targets.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.