The RTL Design Engineer role at Google Cloud in Sunnyvale focuses on shaping the future of AI/ML hardware acceleration through the development of custom silicon solutions. The engineer will work on SoC-level RTL design for data center accelerators, specifically designing RTL IP related to chassis infrastructure. This position requires collaboration with software and hardware counterparts to ensure successful integration and functionality. The role is part of a team that drives innovation in TPU technology, impacting millions of users worldwide.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 2 years of experience in ASIC RTL design, focusing on clocking, reset, or timing-critical RTL development.
• Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

• Create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Evaluate features and their impact in collaboration with architecture and power teams.
• Create test plans to verify and debug design RTL with Design Validation teams.
• Ensure design meets physical requirements and timing closure by working with physical design teams.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.