The Low Power Verification Engineer will work on shaping the future of AI/ML hardware acceleration at Google. This role focuses on driving the development of cutting-edge TPU technology that supports Google's AI/ML applications. The engineer will be part of a team dedicated to creating custom silicon solutions and verifying complex digital designs, particularly in TPU architecture. This position offers the opportunity to contribute to innovations that impact millions of users worldwide.

• Experience in ASIC design and verification.
• Experience with physical verification tools such as DRC and LVS.
• Experience with SystemVerilog or other hardware verification languages.
• Experience with low-power digital design methodologies.
• Experience in design closure on advanced process nodes.
• Experience with EDA tools and design methodologies.

• Define low power verification strategies and methodologies for complex ASIC designs.
• Author comprehensive low power verification plans targeting UPF-defined power domains and states.
• Develop power-aware testbenches and simulation environments using SystemVerilog and UVM.
• Verify power intent utilizing static low power verification tools like VC LP or Conformal LP.
• Run gate-level simulations with power-aware models to validate power-up and power-down sequences.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.